Direct memory access (DMA) engines are devices that are capable of temporarily taking control of a bus and performing data transfers between various devices. Such data transfer may occur between memories, memories and devices, and devices. DMA engines enhance system performance by freeing the microprocessor from having to do the transfer of data itself. DMA engines generally take a lot of gates to build, which can take up considerable space of a die area. Therefore, it will be advantageous to minimize the number of DMA engines on a die.
In addition, in cases where receiver buffers are involved, conventional methods normally utilized a combined context/DMA engine per buffer. One of the drawbacks to this method is that when the DMA engine works on data associated with a particular context, no data associated other contexts would be allowed in the buffer. Therefore, the I/O interface would be forced to wait while the data associated with a particular context were drained out of the buffer. Once drained, the next set of data associated with another context are loaded into the buffer before the combined context/DMA engine is configured. This resulted in long delays on the DMA engine data transfer interface.
As can be seen, there is a need for a system and method that allows maximum utilization of both the receive buffer and the DMA data transmission interface.